A Step-by-Step Guide to Designing an ASIC

Introduction

ASICs are customized hardware developed for a specific application. They usually offer optimum performance, power efficiency, and area benefit over general-purpose processors. ASICs provide the backbone for technologies ranging from consumer electronics and telecommunications to automotive systems and artificial intelligence. This blog will take you through the entire ASIC design flow with its detailed explanation and flowcharts visualizing the workflow.

What is an ASIC?

ASIC is an integrated circuit designed for a particular application. Unlike FPGAs or general-purpose CPUs, ASICs are well-optimized for efficiency in power usage, smaller physical size, and lower consumption of actual power. However, it calls for investing more time and resources in its development process-it is well suited for high-volume production.

ASIC Design Flow Overview

The ASIC design flow consists of the following steps:

1. Specification
2. Architectural Design
3. RTL Design and Coding
4. Functional Verification
5. Synthesis
6. Physical Design
7. Sign-Off and Manufacturing
8. Testing and Validation

Step-by-Step Guide

Step 1: Specification

The first thing in the ASIC design process is specifying its requirements. It ensures that all involved stakeholders, from designers and architects to the end-users, understand what such an ASIC should achieve. Let’s break that down:

1. Functionality:

Begin by defining the ASIC’s intended functions. For example, is the ASIC an image processor, a network packet handler, or an industrial motor controller? This step sets up the rest of the design and ensures that the team completely understands the purpose of the chip.

2. Performance Metrics:

Define the performance objectives, which typically include:

• Speed: At what clock frequency does the ASIC need to function?
• Power Consumption: Target power usage, especially critical for battery-powered or low-energy applications.
• Area Constraints: The maximum size of the chip in terms of cost and feasibility.

3. Interfaces:

Identify what communication protocols or interfaces the ASIC needs to support when interfacing with other components or systems. This may include,

• SPI (Serial Peripheral Interface)-Short-distance communication among devices.
• I2C (Inter-Integrated Circuit)-Low-speed peripherals connecting.
• PCIe (Peripheral Component Interconnect Express)-High-speed data transfer among components.

4. Process Technology:

Select the manufacturing process node based on the best considerations about performance, power, and cost. Such as

• 7nm or 5nm: For high-performance and power-efficient designs like smartphones and processors.
• 14nm or greater: For cost-sensitive or not-so-complex designs such as those used in IoT devices.

Result:

You will have developed a complete design specification document by the end of this step. This is a blueprint for the project, which guides all subsequent design stages and ensures that the final ASIC meets the intended goals.

For insights into real-world ASIC applications, explore this Case Study on ASIC Design Techniques for Multi-Processor System-on-Chip (MPSoC) Development.

Step 2: Architectural Design

With the specifications defined, the following is deciding how the ASIC should be designed to fulfill these requirements. This is the architectural design stage, which plans the overall structure of the ASIC. Let’s break this step up into key activities:

1. Determining Internal Blocks

The first task is to identify the major components or “blocks” that the ASIC will need. These blocks are like building blocks for the chip, each responsible for a specific function. For example:

• ALUs (Arithmetic Logic Units): For performing calculations and logical operations.
• Memory Blocks: For temporary data storage during operations.
• DSPs (Digital Signal Processors): For handling complex operations like filtering, FFTs, or image processing.

Defines each block by the functionality of the chip to ensure they interact correctly with each other.

2. High-Level Data Flow and Control Flow

Design the overall behavior of the ASIC.

• Data Flow: How data is directed between blocks. It may be from memory in a processing block in the ALU, for example, then back to memory.
• Control Flow: How operations are controlled and coordinated, including which block performs what action and when. It defines the control signals and operational sequences.

This step checks that the chip can perform its tasks effortlessly without bottlenecks.

3. Power and Clock Distribution Planning

Power consumption and timing, being critical elements of ASIC design, this stage of planning also involves including:

• Power Distribution: Designing how power is to be delivered to the various blocks in such a way that there is very little loss and operation is very stable.
• Clock Distribution: Providing an efficient clocking structure to synchronize the operations of different blocks. The correct design of clock distribution plays an important role in meeting time requirements and avoiding errors.

Tools Used

High-level design tools are utilized to draw pictures and simulate the architecture:

• MATLAB: For algorithm design and validation.
• SystemC: For system-level modeling and simulation.

Other techniques for pre-design validation of architecture.

Output

The output of this phase is a high-level block diagram that shows all the major components that make up the ASIC, how they interact, and how they meet the functionality specified. This diagram then becomes the roadmap for further design phases where it materializes as a sound structure and purpose for the chip.

Step 3: RTL Design and Coding

RTL design and coding is the step wherein the desired functionality of the ASIC is coded. Here, the register-transfer level is defined by using HDLs like Verilog or VHDL as to how the ASIC would work. Let’s explain this in detail:

What is RTL Design?

At the RTL level, the ASIC is described by:

• Registers: Storage elements for holding data.
• Logic: Perform operations on the contents of the data such as addition, and comparison.
• Data Transfers: Movement of data between the registers and other blocks within a clock cycle

This abstraction provides an environment for simulation, synthesis, and hardware implementation.

Steps in RTL Design and Coding

1. Break up the entire ASIC design into smaller modules

There is one large ASIC design, but it will be broken up into several other, smaller manageable modules.

• Each module embodies a particular purpose (such as an arithmetic unit, memory controller, or communication interface).
• This modular nature makes the design easier to code, test, and debug.

2. Code Each Module with the Desired Functionality

Writing the code using HDL (Verilog, VHDL, etc) to describe the functionalities of each module. For instance:

• ALU module performs addition, subtraction, and logical operations.
• Memory controller module controls read/write operations for data.

Focus on clean, efficient, and synthesizable code, which adheres to the design specifications here.

3. Add Assertions and Constraints for Verification

Add assertions and constraints to the RTL code. These are rules or checks that are embedded in the code to ensure the behavior of the design.

• Assertions might check whether signals stay within valid ranges.
• Constraints will specify a limit on timing, area, or power, which will be followed by synthesis tools later.

Outcome

• In the end, this stage produces synthesizable RTL code, which is a representation of the ASIC’s functional behavior. That is to be processed and optimized further into a gate-level design in the following stages.
• At the end of this stage, the RTL code is ready for simulation, verification, and eventual transformation into physical hardware.

For more on the skills and expertise required for this step, refer to Skills You Need to Build a Career in the Semiconductor Industry.

Step 4: Functional Verification

The RTL code is functionally verified to confirm that it performs the desired behavior according to the design specifications. This step catches any errors in functional behavior and corrects them before proceeding to the subsequent stages.

Major Activities of Functional Verification:

Testbench Creation

• Testbench: A testbench is a simulation environment that allows communication with the RTL code to test its behavior.
• Tools like ModelSim or QuestaSim are used to simulate the RTL’s behavior for many different inputs and conditions.
• For instance, if the ASIC is a calculation chip, the testbench checks whether adding, subtracting, and multiplying work correctly under any conditions.

Coverage Analysis

• Coverage analysis determines how much of the design has been exercised in the tests. Functional coverage ensures that all features of the design are used.
• Code coverage verifies that all the RTL lines are executed at test time.

Debugging

• All the functional bugs reported by the simulator are corrected at this stage.
• Trace signals, detect errors, and correct the RTL to behave as intended

Output:

• RTL verified to implement functionality and now synthesis ready.

Step 5: Synthesis

Synthesis is the process of converting the proven RTL code into the netlist that describes the design using logic gates. That netlist would map the design to the standard cells that the desired process technology has given.

Steps in Synthesis:

Apply Constraints

Constraints are provided to guide the synthesis tool. These include:

• Timing constraints: Specify the clock frequency the design must achieve.
• Power constraints: Define limits on power consumption.

Area Constraints

• Limit the physical area of the design.

Optimize Design

• The synthesis tool optimizes the netlist based on the design while balancing performances, power, and area.
• For instance, any redundant logic is removed and gates are selected to pass the timing with the power budget not breached.

Tools Used

• These popular tools are Synopsys Design Compiler and Cadence Genus.

This step plays a critical role in creating cost-effective and efficient chips. To understand how to optimize this step in collaboration with industry experts, read The Advantages of Partnering with Top Semiconductor Distributors.

Step 6: Physical Design

The physical design stage consists of the ASIC’s physical layout, which reflects the placement of hardware components and wiring on the chip.

Physical Design Steps

Floorplanning

• Floorplanning outlines the layout of the chip in which major functional blocks and input/output pins are placed.
• Proper floorplanning minimizes wiring complexity and ensures efficient power distribution.

Placement

• Place all standard cells, which include logic gates, flip-flops, etc., on the chip within the assigned regions.
• Optimize the placement of the design such that timing, as well as area constraints, are met.

Routing

• Use the metal layers to connect the placed cells to the needed signal paths.
• Routing minimizes delay and prevents interference between signals.

Timing and Power Analysis

• Perform detailed timing analysis to ensure timing closure of the design
• Optimize power to minimize ‘hotspots’ and provide stable operation

Tools Used:

• Common tools are Cadence Innovus and Synopsys IC Compiler.

Outcome:

• A complete GDSII layout file, which is the final file sent to the foundry for manufacturing.

Step 7: Sign-Off and Manufacturing

Before the ASIC is given to the foundry for fabrication, it is put through a series of closing checks to make sure that it meets the requirements of the foundry.

Important Sign-Off Tasks:

DRC Design Rule Check

• Shows that the layout adheres to the manufacturing rules provided by the foundry, including minimum distances between wires or layer thickness.

LVS Layout vs. Schematic

• It checks that the physical layout is identical to the original gate-level netlist and does not have any place where the wire delay can propagate during the physical design stage.

Parasitic Extraction

• This counts for resistive and capacitive effects of the wires which impact the signal timing and power consumption.

Result:

• After these checks, the GDSII layout file is transmitted to the foundry to fabricate the ASIC chips.

Step 8: Testing and Validation

After the ASIC chips are fabricated, they undergo intense testing to ensure that they meet specifications and to assure that they work correctly in operational conditions.

Precisely, key testing activities include:

Functional Testing

• Tests whether the ASIC correctly carries out intended functions
• The test is done using a variety of input values and scenarios.

Burn-In Testing

• Various stresses in the form of temperatures and voltages are applied to the ASIC to simulate its long-term usage and detect reliability flaws.

Volume Testing

• Testing of a high number of chips in batches, while maintaining the desired yield rates and detecting manufacturing defects.
• Failed chips are rejected or graded according to performance

Outcome:

• fully validated ASIC chips tested and ready for use in their respective application environments.

Challenges in ASIC Design

1. High Cost: Mask sets for fabrication are expensive.
2. Verification Complexity: Ensuring zero functional bugs is challenging.
3. Power Optimization: Balancing performance with low power consumption.
4. Long Development Time: ASIC design can take years to complete.

Conclusion

ASIC design is a very minute process with various skills of learning that commence from architectural planning, placement and routing, and final testing. Although difficult, the performance, efficiency, and customization advantages of ASICs make them a must-have for applications at an advanced level of performance. Next, you can work your way through the complexity of the ASIC development process and reach a successful design when you have this structured design flow. Vendors, are you interested in learning more? Check out additional blogs and case studies on Nanogenius Technology’s website.