Key Learnings of the ASIC Design Journey

A case study of Nano Genius Technologies

ASIC design is one of the most specialized and high-stakes areas of semiconductor engineering. Undergoing intense innovation in these relatively niche branches, at Nano Genius Technologies, one of the leading manufacturers of semiconductors in India, we dedicated ourselves to pushing the boundaries of innovation through custom ASIC solutions tailored towards meeting the varied needs of our clients.

The case study reflects our experience developing a next-generation ASIC for a smart IoT platform. It captures the challenges, decisions, and outcomes that formed our journey and gives actionable insights into anyone venturing into ASIC development. We further extend this by elaborating on the role of ASIC design consultation in bridging the gap between client requirements and technical implementation.

The Initial Challenge: Why ASIC?

The story begins with an international IoT company that was not satisfied with the out-of-the-box solutions of the market. Their devices required:

1. High energy efficiency to meet IoT constraints.
2. Compact form factor for wearable technology.
3. Superior computational capabilities for real-time edge processing.

After trying several FPGA-based and commercial SoC solutions, they experienced power, latency, and scalability issues. This is when they approached Nano Genius Technologies for an ASIC-based solution.

Real-World Insight

The primary reason is because ASICs are very expensive to design and the initial outlay is quite high. In this case, we were able to demonstrate that coming into a custom silicon design could realize 50% better power efficiency and 40% cost savings over the lifetime of the product. Read more on the ASIC vs FPGA debate.

Step 1: The Consultation Process

An ASIC design consultation is a feasibility and cost-effectiveness study for producing a custom chip with real technical benefits. Our consultation started with a phase called requirement gathering, and we worked closely with the client to define the following parameters:

1. Target Specifications: Including clock speed, power budget, and area constraints.
2. Use Case Scenarios: Tailoring the design for Bluetooth Mesh communication and edge AI workloads.
3. Volume Forecasts: Estimating production volumes to justify ASIC investment.

Outcome of Consultation

After an intense review, we concluded that a 28nm technology node was appropriate for achieving balanced power efficiency with the cost of fabrication. This conclusion emerged after diving into EDA tools, IP licensing options, and scaling their use cases.

To get a thorough resource to start an ASIC project, check this out.

Step 2: Set up for Development

1. Selection of Tools: ASIC design success heavily relies on the choice of the EDA tools. For this project, we used:
   1. Synopsys Design Compiler for Synthesis.
   2. Cadence Innovus for physical design.
   3. Mentor Graphics Questa for simulation and verification.

It reduced the RTL-to-GDSII flow and allowed us to meet such aggressive timelines without compromising on quality. Know the best EDA tools.

2. IP Integration: We used pre-verified IP cores that diminish the design time for blocks like commonly applied wireless communication protocols, for instance,
   1. Bluetooth Mesh stack protocols.
   2. Standardized cryptographic modules.

Pre-verified IP not only accelerated development but also reduced verification overhead.

Step 3: Mitigation of Key Challenges:

Challenge 1: Clock Domain Crossing (CDC)

Thus, multiple clock domains become a norm in IoT ASICs, and hence data synchronization can easily go wrong. We used advanced CDC verification tools to identify and mitigate such data-synchronization issues early in the design cycle.

Challenge 2: Power Optimization

One of the client’s critical requirements was ultra-low power consumption. To achieve this, we adopted:

• Dynamic Voltage and Frequency Scaling (DVFS) for performance adjustment according to the amount of workload.
• Clock Gating was used to reduce dynamic power consumption in idle modules.
• All these techniques brought down the power consumption of the chip by more than 30%.

Read more on low-power ASIC techniques.

Challenge 3: Verification Complexity

Verification was consuming nearly 60% of the project timeline. Using UVM (Universal Verification Methodology), we created reusable test benches and simulated billions of test scenarios, thereby ensuring design reliability.

Step 4: Tape-Out and Manufacturing

The biggest milestone is tape-out, after several months of iterative design and verification, we collaborated with a leading global foundry, TSMC, to fabricate the chip.

Post-Silicon Validation: Once we received the first silicon samples, our attention went to post-silicon validation. It was primarily to verify that the design translated into reality. We put it through thorough testing in various environmental conditions – high temperature, low voltage – to ensure its reliability.

Mass Production: With the validation now in hand, mass production could begin, and over 1 million units would be shipped within the first year.

Step 5: Real-World Deployment

The ASIC was deployed on the client’s IoT platform and delivered:

• 60% higher compute rates for edge AI workloads.
• 50% longer battery life, which is greatly needed for wearables.
• 25% in device size reductions make wearables smaller, and easier to carry around.

Client Testimonial

“Our engagement with Nano Genius Technologies was revolutionary. Their ASIC design consulting and delivery experience helped us meet all the KPIs,” said the client’s Chief Technology Officer.

Key Takeaways from ASIC Journey

1. Planning is Important: Engagements of clients beforehand to discuss deeply at this stage helped avoid redesign after the stake has been levied.
2. Verification is Not Up for Bargain Discussion: The success or failure of ASIC projects is validated through robust verification strategies. Heavy investments in UVM and Simulation tools yielded time and money saved during manufacturing.
3. Tap into India’s Semiconductor Talent Pool: Class talent is readily available here, and topper research institutions are giving India exposure as an emerging global semiconductor innovation hub.

Click here for the article to get more information about India in the semiconductor market.

How Nano Genius Technologies Can Assist You

At Nano Genius Technologies, we bring over a decade of expertise in ASIC design consultation and implementation. Our proven track record comprises custom silicon solutions for the IoT, automotive, and telecommunications industries.

Learn more about our ASIC services.

If you’re considering your own ASIC project, here are some resources to get started:

• Understanding ASIC Design
• Best Practices for Semiconductor Manufacturing
• IoT and Custom Silicon Solutions

Frequently Asked Questions (FAQs)

1.     How long does it take to design an ASIC?

The design cycle typically takes 12–24 months, depending on complexity. Factors like verification time and manufacturing availability can influence timelines.

2.     What is the typical cost of an ASIC project?

Costs vary widely but typically include EDA tool licenses, IP cores, engineering hours, and fabrication expenses. A detailed feasibility study ensures ROI for your specific use case.

3. How do ASICs compare to FPGAs in IoT applications?

Though FPGAs are flexible, ASICs are more efficient in terms of power consumption, performance, and cost at scale, which is a characteristic of high-volume IoT applications. To access more case studies, go to Nano Genius Technologies Case Studies.